Job description :

• 5+ years of Experience in Physical Design
• Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
• Own complete PD execution of Sub-systems/Sub-chips instantiating/integrating multiple other Physical partitions.
• Own partition floorplanning for optimizing blocks for Power, Performance and Area.
• Collaborating and influencing various aspects of PD Methodology will also be key requirement in this role.
• Have close collaboration with RTL team (RTL2PD liaison) to help drive and resolve design issues related to block closure.
• Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
• Implement robust clock distribution solutions using appropriate methods that meet design requirements.
• Additionally drive key pieces of PD implementation methodology or specific areas such as Clocking/Low power optimization/Power & Performance methodology.
• Make independent and good technical trade-off decisions between power, area, and timing (PPA).
• Be able to guide and coordinate with all sub-partitions PD to be able to take the Sub-chip through PD (construction through signoff) closure.
• Partner closely with PD flow/CAD team and PD methodology team.
• Be fully hands-on in your individual ownerships as individual contributor and collaborate cross-team on all aspects of SC/SS execution, integration & delivery.
• Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers.
• Mentor junior engineers on technical issues.