The growing demand for adaptive and efficient hardware solutions has fueled the interest in Application specific integrated circuits(ASIC) s reconfiguration. While ASIC’s are designed for specific purpose and optimized in terms of power and area than Field programmable gate array(FPGA’s), they lack flexibility required for diverse applications. This paper provides a novel approach for the reconfiguration of ASIC using combinational logic blocks. It provides a dedicated reconfigurability block that can be incorporated into ASIC architecture that provides dynamic reconfiguration. The proposed design is implemented in cadence virtuoso and tested under ADE L environment. The results are demonstrated in this paper. This work paves the way for developing adaptable hardware that combines the inherent advantages of ASIC’s with enhanced reconfigurability. In this paper, the hardware utilizes 11.97E-6 watts of power and the delay between input and output is 320.0E-9 seconds.